The staff is liable for the verification of subsequent era Built-in Excessive Pace RF Transceiver SoC Merchandise. These merchandise includes of excessive efficiency Transceivers containing Built-in RF Sign chain elements with excessive diploma of digital integration. The staff handles verification of the merchandise which embody digital sign processing datapaths, excessive pace interfaces, embedded microprocessor techniques and DFE features that go into these merchandise.
As an skilled Senior engineer on this group, candidate will work with the newest verification methodologies on designs starting from particular person blocks to chiplevel and system stage verification for these SoCs at utility stage.
- Verification of complicated designs and subsytems utilizing essentially the most forefront methodologies.
- Affect the choices on methodolgies to be adopted for the verification.
- Architect the testbench and develop in UVM and Formal primarily based verification approaches.
- Combine the block testbench at chiplevel UVM setting and confirm integration.
- Outline testplan, checks and verification methodology for block / chiplevel verification.
- Work with design staff in producing test-plans and closure of code and useful protection.
- Steady interplay with analog co-sim and firmware staff in enabling toplevel chip verification elements.
- Assist post-silicon verification actions of the merchandise working with design, product analysis and functions engineering staff
- BTech/MTech diploma in Electrical/Electronics/Pc science from reputed institutes
- 3 – 8 years of expertise in design verification with UVM and constrained random, protection primarily based verification approaches.
- Adaptability to study finish utility/techniques and map into sensible verification take a look at plan at system stage
- Wonderful debugging and analytical expertise
- Data of Assertion primarily based formal verification might be a plus
- Good verbal and written communication expertise
Firm: Analog Units